1. Field of the Invention
The present invention relates to a clock generator used in a logic circuit which operates with switching between two clocks having different frequencies.
2. Description of the Prior Art
A conventional logic circuit system utilizes high frequency clock (first clock) and low frequency clock (second clock) for the purpose of lower current consumption at the circuit. Specifically, the first clock with higher frequency is used when rapid operation is required and the second clock with lower frequency is used for lower speed operation with lower power consumption when rapid processing is not necessary. Such switching between the clocks saves power consumption.
In such a logic circuit system, sufficiently stable oscillation or stable frequency is required at the second clock when the system switches from the operation using the first clock to the operation using the second clock. For this, when switching from the first clock to the second clock, the timer controlling the first clock currently in operation keeps certain time after the start of oscillation at the second clock so as to wait for the second clock oscillation to become stable before actual switching to the second clock.
FIG. 4 is a timing chart for conventional clock switching. In the figure, (a) represents the oscillation of the first clock (CLK1), (b) represents the oscillation of the second clock (CLK2) and (c) is the clock switching signal. When this clock switching signal changes from H (high level) to L (low level), the system clock switches from the first clock to the second clock.
Referring to the timing chart in FIG. 4, the logical circuit system is operating according to the first clock generated by a clock generation circuit at the time T0, with the other clock generation circuit for the second clock terminated. A clock control circuit controls so that clock switching starts at the time T1 with causing the second clock to start oscillation. Thus started second clock oscillation becomes sufficiently stable at the time T2. The clock control circuit is in advance given a time (T3-T1), which takes into account the time (T2-T1) for stabilization of the second clock oscillation. The clock control circuit activates the timer at the time T1 to keep time and makes the switch signal to the low level at the time T3 so as to switch the system clock to the second clock. Then, after a certain period, the clock control circuit starts termination operation of the first clock at the time T4 and completely stops the first clock at the time T5. Thereafter, the logical circuit operates according to the second clock until the next clock switching.
In this series of operations, the time (T3-T1) from the start of oscillation at the second clock until the switching of the system clock to the second clock is set considering various environmental conditions in circuit designing stage. This is because the time until stabilization varies depending on environmental conditions such as oscillation start characteristics of the oscillation and the temperature, in case of the second clock with a lower frequency. If a timer keeps a certain time for clock switching as described above, the switching time is set more than the time actually required from oscillation start until the stabilization of the oscillation after consideration of various conditions.
However, oscillation stabilization time (T2-T1) of an oscillation circuit using a crystal oscillator commonly used in conventional systems vary depending on oscillator, degradation in time and current temperature conditions ranging from some milliseconds to some seconds. For an oscillation circuit generating low frequency clock, in particular, the time from oscillation start to frequency stabilization fluctuates quite largely. For example, in the case of an oscillation circuit which generates a clock with a frequency of about 32 kHz, it usually requires only a couple of seconds but sometimes can require some dozens of seconds at the worst depending on the environmental conditions. Therefore, it is difficult to set a uniform time period for all oscillation circuits manufactured in mass-production, for the time kept at the time of switching. It is also difficult to properly set a switching time for an oscillation circuit to ensure proper clock switching operation under any environment.
This means that, when the timer keeps certain time and switches the system clock, the second clock frequency may not have reached stable status. Forced clock switching causes the system to operate according to instable clock, which may result in errors, getting out of control or stopping.